Apparatus for interleaving and de-interleaving data

ABSTRACT

A novel interleaver-de-interleaver is provided which is adapted to store bits of a data stream after being error encoded. The data bits are stored in a random access memory in addresses identifiable by an array of columns and rows. The interleaver comprises address pointer means and logic for reading the data bits out of the memory addresses in a predetermined reordered sequence to provide a quasi-random pattern sequence of data bits which when transmitted are substantially immune to periodic bursts of radio frequency interference signals.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to apparatus for interleaving transmitted data.More particularly, the present invention discloses novel apparatus forinterleaving and de-interleaving digital data that effectivelyrandomizes channel burst interference.

2. Description of the Prior Art

Radio frequency waveforms employed to transmit communication data havebeen jammed or interfered with by radio frequency interference (RFI)signals. It is well known that high energy burst of RFI signals orperiodic pulsed RFI signals can be made so strong as to completely masktransmitted communication data signals.

It is also well known that interleaving and de-interleaving apparatuscan be employed to improve the performance of the transmitted datasignals in the presence of burst of RFI signals. When the transmitteddata is interleaved, the bits of data may be so distributed over a timeperiod that the RFI signals do not mask or block sequential bits of theoriginal data stream. When the interleaved data bits are de-interleavedat the receiving station, the receive blocks of data appear to haverandomized bit errors rather than having broad ommissions of data whereburst of RFI signals have occurred. The receive blocks of data bits withbit errors may be corrected by employing a proper type of errorcorrection encoder and decoder that will correct the bit errors.

Row-column interleavers are known where a series stream of data bits arerecorded sequentially in a memory array as horizontal rows of data bits.When the data bits are read out of the memory array, they are read outas vertical columns of data bits which effectively reorders the sequenceof the series stream of data bits. Convolution interleavers are alsoknown in which a data stream is effectively stored in a shift registerand selected bits from different bit positions are read out of the shiftregister to reorder the stream of data bits. Row-column interleavers andalso convolution interleavers are not as effective against periodicburst of RFI signals as would be desired.

Ira Richer has described a block interleaver in the March, 1978, IEEETransactions on Communications, Vol. 26, No. 3. The described blockinterleaver effectively takes the block of data bits in a series streamand changes the original serial positions to a predetermined series ofnew positions similar to the afore-mentioned convolution interleaver.While this block interleaver is described as providing a linearcongruential sequence of data bits which perform well in a useful rangeof periodic RFI duty cycles and repetitive rates it too leaves much tobe desired.

It would be desirable to provide an improved or optimized interleaverand de-interleaver for use in a transmitting system subject to periodicburst of RFI timing signals which is effective over an unrestrictedrange of periodic RFI repetitive rates and jamming duty cycles up totwenty-five percent.

SUMMARY OF THE INVENTION

It is the principal object of the present invention to provide a noveland improved interleaver and de-interleaver for a data transmissionsystem which is subject to radio frequency interference (RFI) signals.

It is another principal object of the present invention to provide anovel row-column interleaver and de-interleaver for use in a datatransmission system subject to RFI jamming signals which may beeffective over an unrestricted range of RFI repetitive rates andextended duty cycles.

It is another object of the present invention to provide an improvedinterleaver and de-interleaver which is easy to implement withcommercially available components.

It is another object of the present invention to provide an improvedinterleaver and de-interleaver which may be implemented in hardware orsoftware form.

It is yet another object of the present invention to provide a novelrow-column interleaver and de-interleaver having a new and novelpermutation for reordering data bits in columns or rows and forreordering columns or rows of data bits in an array of columns and rows.

It is a general object of the present invention to provide apredetermined permutation for reordering and rotating bits and columnsand rows.

It is a further object of the present invention to provide a novelon-line interleaving and de-interleaving apparatus which optimizes thedelay of the original data stream being recorded.

According to these and other objects of the present invention to beexplained in greater detail hereinafter, there is provided aninterleaving apparatus intermediate an encoded original data stream anda transmitter. The interleaver is adapted to store the bits of the datastream in a memory comprising a plurality of memory address positionsarranged as an array of columns and rows. The interleaver comprisesaddress pointer means for reading the data out of the address positionsin a reordered sequence to provide a predetermined quasi-random patternsequence of data bits which are substantially immune to periodic burstof radio frequency interference signals.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating a typical environmentalapplication of the present invention interleaver and de-interleaver;

FIG. 2 is a schematic diagram showing a block of 64 data bits before andafter being subject to a high energy burst of radio frequencyinterference signals;

FIG. 3 is a block diagram showing a preferred embodiment buffer memoryand address pointers employed in the interleaver and de-interleaver ofthe present invention;

FIG. 4 is a schematic table of an 8×8 memory array showing the addresspositions of data bits before permutation;

FIG. 5 is a schematic table of the 8×8 memory array of FIG. 4 showingthe address positions of data bits after permutation;

FIGS. 6A and 6B are schematic tables of an 8×8 memory array showing theposition of the address bits during and after dual orthogonalpermutation;

FIGS. 7A and 7B are schematic tables of an 8×8 memory array showing theposition of the address bits during and after another form of dualorthogonal permutation; and

FIG. 8 is a block diagram showing another preferred embodimentinterleaver and de-interleaver.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Refer to FIG. 1 showing in block diagram a typical environmentalapplication of the present invention. The data source 10 comprises anyseries form of data bits to be transmitted. The source of data bits areerror correction encoded at block 11. which also includes means forrecognizing the start of a block and generating a block start signal online 12. The encoded stream of data bits is passed through theinterleaver 13 and subsequently processed and transmitted by transmitter14 on line 15 which may comprise an antenna or a channel 16. It will benoted that an air or line channel 16 is also referred to as a channel.The receive signals on line 18 have been subject to a burst of radiofrequency interference signals as indicated by the input line 17. Thereceive signals are processed by receiver 19 and passed throughde-interleaver 21 where they are error decoded in decoder 22 beforebeing presented as an output to the data sink 23 or utilization device.

Refer now to FIG. 2 which shows in a schematic diagram form the effectsof interleaving and de-interleaving. FIG. 2A represents a serial streamof sixty-four data bits numbered in the order of sequence in which theyappear. Pulse 24 represents a high energy burst of radio frequencysignals which is so strong as to effectively block out the data bitsbeing presented at positions 25 through 40. Ordinarily, if the signalsare not processed, the blocking out of twenty-five percent of the datain a block is effective to disrupt the transmission of communicationsdata. FIG. 2B represents a reordering of the positions of the data bitsof FIG. 2A employing bit rotation permutation as will be explainedhereinafter with regards to FIG. 5. FIG. 2C illustrates thede-interleaved stream of data as it would appear leaving thede-interleaver 21 employing the afore-mentioned simple bit rotationpermutation.

FIG. 2D represents a different form of interleaving which can beperformed by interleaver 13 and is referred to hereinafter as dualorthogonal permutation. FIG. 2E illustrates the data stream which wouldbe generated at the output of de-interleaver 21 when employing thepreferred embodiment dual orthogonal permutation to be explained indetail hereinafter.

In FIG. 2B, the data bits which were interleaved starting with data bit20 up to data bit 45 are completely blanked out. In the reorderedsequence after de-interleaving, it is noted that eight pairs of bitshave been blocked out or interferred with but are separated one from theother in a manner which permits error correction encoding and decodingto make allowance for these errors.

Refer again to FIG. 2D showing a different reordering or sequence ofdata bits in which the data bit starting with bit 23 and ending with thebit 43 are blanked out by the pulse 24.

After these interleaved data bits are de-interleaved and placed in theiroriginal order as an output of de-interleaver 21, it is noted thatsixteen single error or bit ommissions are presented which are mucheasier to correct by standard error encoding and decoding means.

FIG. 2E has been presented to simplify the explanation of the presentinvention. The bit error distribution shown in the figure issubstantially periodic. However, as the interference burst signal 24becomes more repetitive the bit errors will be distributed in a morerandom or quasi-random pattern and such patterns are capable of beingcorrected by error correction encoding and decoding apparatus such asconvolution encoding employed with Viterbi decoders.

FIG. 3 is a block diagram showing the structural elements employed in aninterleaver and in a de-interleaver. The periodic and regular sequenceof data bits appearing on the input data line 26 will be presented toboth data or memory arrays 28 and 29 even though only one memory arraywill be effective to accept the data being presented on line 26 at anyone time. The block or frame synchronization signal on line 27 is beingpresented to the D type flip-flop 30 so as to present a high output oneither the Q or Q output lines 32 or 31 respectively. When the highoutput from Q is presented on line 31 to the write enable input ofmemory array 28, the series of signals being presented at the write line26 to memory array 28 are sequentially read into the memory array 28 atthe sequential addresses which are being presented at address pointerline 33. The addresses appearing at pointer line 33 are generated byaddress counter 34 which is being driven by clock signals on line 35 tocause addresses to appear on line 36 to the address multiplexer 37. Whenthe Q signal from the flip-flop 30 is high on line 31, not only does itenable writing to memory array 28 but it sets the address multiplexer 37so as to cause the sequential addresses from address counter 34 toappear on line 33. When the Q signal on line 31 is low so as to disableaddress multiplexer 37 and writing into memory array 28, there is a highQ signal on line 32 which enables the memory array 29 and the addressmultiplexer 38. The address counter 34 now presents via line 36 toaddress multiplexer 38 a sequence of addresses which are passed throughmultiplexer 38 and presented via line 39 to memory array 29. It will beunderstood that memory array 28 is having data bits stored in the memory28 while memory array 29 is having data bits read out and vice versa.Thus, it will be understood that when the write enable line to memoryarray 28 or 29 is low or inactive, the memory array will be enabled forreadng. Assume now that memory array 28 has a complete block ofinformation stored therein as a result of data bits arriving on dataline 26. After the memory is loaded the address multiplexer 37 is resetbecause the set line 31 is low, thus enabling the address line 41 fromaddress ROM 42 at MUX 37. Even though the address pointer line 41 isactive, the signal being presented at address multiplexer 38 is blockedbecause the address multiplexer is being set by line 32. The output orpointer addresses on line 41 are passed through address multiplexer 37and presented as read out addresses to memory array 28 which causes thedata bits in the address so designated to appear on data output line 43.The data bits on line 43 are applied to AND gate 44 which is held in theenabled position by the high signal from the Q output on line 32 causingthe data bits being read from memory array 28 to appear at AND gate 44and at OR gate 45 and on data output line 46. It will be understood thatthe address counter 34 is presenting a complete sequence of addresses online 36 which are applied to address ROM 42 so that the new addresses online 41 will completely read out all of the bit addresses in memoryarray 28 before flip-flop 30 changes state to reverse theafore-mentioned procedure in which data stored in memory array 29 willbe read out through AND gate 47 and OR gate 45 on to data output line46. While the information in memory array 29 is being read out, the datainput on line 26 is being written into memory array 28.

It will be understood that the sequence of addresses from addresscounter 34 on line 36 are in a regular binary sequential order and thatthe new addresses that are being read out of the address ROM 42 are in apredetermined quasi-random sequence as will be explained hereinafter.Address ROM 42 may be a non-eraseable ROM or may be a programmederaseable ROM as the case may be. The effect of address ROM 42 is toserve the purpose of a look up table. It is well known that a smallcomputer or processor can be programmed to present look up tableaddresses, however, the speed with which the communication systems areto be operated makes it highly desirable to use an address ROM whichoperates in a few microseconds.

Refer now to FIG. 3 showing schematically in column and row array formthe numbered bit positions for an 8×8 memory array. It will beunderstood that the memory arrays to be used in the present inventionare preferably much larger than an 8×8 array and are usually defined asa 2^(n) by 2^(n) array where n is an interger. In a 64×64 array thevalue of n would equal six.

In the preferred embodiment reordering or permutation, the amount of bitrotation within a column-row or the value of a new column-row position(NP) is equal to a number defined by the old position (OP) plus one timeone-half of the old position. Thus, NP=(OP/2)(OP+1). The old positionsstart with zero and are numbered up to N-1, thus, in the 8×8 array ofFIG. 4, the old positions of zero, one, two, three, four, five, six,seven produce bit rotations of, or new column-row positions of zero,one, three, six, two, seven, five and four respectively. It will beunderstood that in applying the permutation formula the resultant newposition number must be reduced to modulo N.

Refer now to FIG. 5 showing in schematic array form the new position ofthe data bits after being rotated. In FIG. 5 the individual bits arerotated according to the above-mentioned permutation within columns.Thus, in the zero column of FIG. 4 the bits are not rotated. In thefirst column of FIG. 4 the bits in column one of FIG. 5 are rotated oneposition, thus, the number two bit which appear in the zero row has beenrotated one bit position and now appears is row one. It will beunderstood that all of the other bits in column one of FIG. 5 arechanged one position (rotated one bit position) according to thepermutation desired. Similarly, the bits in column two have been rotatedthree bit positions, thus, the number three bit which appeared in rowzero of column two now appears in row three of column two in FIG. 5.Similarly, all of the other bit positions in column two of FIG. 5 arerotated three bit positions. The third column of FIG. 5 has the bitpositions rotated six bit positions or down six rows. The bit positionsof column five have their bits rotated seven positions. The bitpositions in column six have their bits rotated five positions and thebits in column seven of FIG. 5 have their bits rotated four positions.It will be understood that the terminology being applied herein usingrows and columns are interchangeable so far as the application of thenovel permutation is applied.

Refer now to FIG. 6A showing an implementation of column rotationemploying the above-mentioned permutation. To apply the permutation tothe column rotation, the complete column is taken from its old positionand placed in a new position. Using the above-mentioned permutation, thecolumn zero remains in the zero column position and the column oneremains in the one column position. However, the two, three and fourcolumn positions now appear in the three, six and two column positionsand similarly, the old five, six and seven column positions now appearin the seven, five and four column positions. Having performed thispermutation of rotation of columns we may now apply the bit rotation tothe columns as explained with reference to FIG. 5. Applying the samepermutation to rotation of bits within columns the change from FIG. 6Ato FIG. 6B shows the result of the bit rotation of the array afterhaving performed on it the column rotation. It will be noted that therotation of columns and rotation of bits may be referred to as dualorthogonal permutation. By performing dual orthogonal permutation thedistribution of the bits within columns or rows more closely approachesa quasi-random distribution than was heretofore performed with prior artrow-column interleavers.

Having explained how the permutation and reordering of bits has beenderived for FIGS. 5 and 6B it will be appreciated that theafore-mentioned distribution pattern shown in FIG. 2B and FIG. 2D arerepresentative of FIGS. 5 and FIG. 6B respectively.

Refer now to FIG. 7A which is a schematic array in column and row formin which the preferred embodiment permutation has been first applied bybit rotation in FIG. 7A and then the same permutation has been appliedin the orthogonal direction using bit rotation to achieve thedistribution shown in FIG. 7B. Using the above-mentioned permutation thezero column bits are not rotated. The bits in column one are now rotatedin the up direction row (bit) position and the bits in the two columnsfour, five, six and seven are respectively rotated in the up directionsix, two, seven, five and four bit positions as explained hereinbefore.It will be noted that the bits shown in FIG. 7B have been rotated fromthe position shown in 7A according to the above-mentioned permutation.For example, the bits in the zero row are not rotated but the bits inthe number one row are rotated from left to right by one bit position.Similarly, the bits in rows two, three and four are rotated from left toright by three, six and two bit positions respectively. Similarly, thebits in rows five, six and seven are rotated from left to right byseven, five and four bit positions respectively. The bit positions ofthe columns of FIG. 5 were rotated down using the above-mentionedpermutation and the bit positions of the columns in FIG. 7A have beenrotated up using the above-mentioned permutation. As long as theabove-mentioned permutation is done in accordance with the preferredpermutation, it does not change the desired distribution whether therotation is made up or down or right to left.

FIGS. 5 to 7 show in array form the desired bit positions after beingrotated according to the desired permutation. In order to achieve thedesired results described hereinbefore, it is necessary to read thesequence of bits out by reading the columns from top to bottom and fromleft to right as would be done in a row-column interleaver. It will alsobe noted that the schematic representation shown in FIG. 2D may beproduced by reading the columns zero through seven from top to bottom.That is column zero reads one, nine, seventeen, etc. through to bitfifty-seven and column one starts with bit fifty-eight and ends with bitfifty. Thus, it will be understood that the address ROM 42 shown in FIG.3 is preprogrammed to be interregated by the sequential addresses fromaddress counter 34 appearing on line 36 and will produce new addresseson output line 41 in the desired column by column sequence read outwhich was discussed hereinbefore with regards to FIGS. 5 to 7. Theaddress ROM 42 acts as a high speed look up table to define theaddresses desired on output line 41.

FIG. 8 is a block diagram of another preferred embodiment interleaverand de-interleaver. Data being supplied the interleaver 50 is encodeddata being presented on line 51 which is clocked into flip-flop 52 byclock pulses on line 53. When acting as an interleaver 50, the sequenceof operations is similar to that explained with regards to FIG. 3 inthat there is one block time delay required before the informationwritten into memory is read out. However, the present embodimentinterleaver and de-interleaver requires only half the amount of RAMmemory as required in the embodiment shown in FIG. 3. Assume that thetwelve bit address counter 54 has produced the proper sequence ofaddresses on line 55 and that data appearing on line 56 to the RAMmemory array 57 has been stored by rows as explained hereinbefore withregard to FIG. 4.

When the first block of information is loaded into memory 57, a terminalor end condition signal is produced on line 58 which is applied tocontrol means 59. Control means 59 responds with a parallel entry signalon line 61 which instructs the address counter 54 to take its addressesfrom ROM 62.

After the first block of information is loaded in linear fashion intothe memory 57, the second block of information is written or loaded inmemory 57 in random fashion as the first block of information is beingread out of memory 57.

Thus, for example, when applying the random sequence of addresses asshown in FIG. 6B, the ROM 62 produces the quasi-random sequence one,nine, seventeen, etc. to address memory 57 as shown in column zero andproceeds through the columns one through seven reading the sequence fromtop to bottom as shown in FIG. 6B. As each additional address locationis presented on line 55 to memory 57, the next sequential address isbeing presented on line 63 to address counter 54.

To perform the read out and read in sequentially during each of the bittimes, the clock pulses on line 53 are divided into a high level or readportion 64 and a low level or write portion 65.

During the read portion 64 of a bit time, the data at the addresslocation on line 55 is read out on line 66 and stored in flip-flop 67 atthe end of the read period 64. At the end of the read period 64 theclock signal is producing a negative going edge pulse on line 68 whichis inverted at inverter 69 and appears as a positive clock pulse inputat the clock side of flip-flop 67 causing the data to be presented onoutput line 71.

While the same address on line 55 is being presented to memory 57, thedata on line 56 is written into memory 57 during the write portion 65 ofthe same bit time. The write portion of the data bit time 65 is a lowsignal which is presented on line 72 to the write enable input of memory57, thus permitting the data present on line 56 to be written into thesame memory address being presented on line 55. For example, referringto FIG. 6B and FIG. 8, when the address on line 55 is pointing to theaddress location one, the address location one as an input to ROM 62produces the next address or address nine as the output on line 63. Whenthe end of the bit time occurs and the positive going edge of the databit time as shown at point 73 occurs, the address input on line 63 tothe counter 54 is stored in the buffer of counter 54 and also presentedas an output on line 55. After the data on line 56 is written into thelast address location 29, at the end of the block, an end of blocksignal is produced on line 74 which causes the control means 59 todisable the parallel entry signal which was present on line 61 thusdisabling the parallel entry from the ROM from the next block ofinformation to be presented.

It will now be understood that the information is located inquasi-random form in memory 57 and that when the address counter 54addresses the memory 57 in the afore-mentioned sequential form that theinformation being produced on line 66 is going to be in quasi-randomform in the manner in which it was identified with regard to FIG. 6B. Atthe end of this block a new end of block signal is produced on line 58which causes the control means 59 to again produce the parallel entrysignal on line 61 which causes the next block of information to beidentified by the ROM 62. Having explained how the interleaver operateswith regard to every other block of information, it will be understoodthat only one memory array 57 is required using the FIG. 8 embodimentwhereas the FIG. 3 embodiment required two memory arrays.

When the FIG. 8 embodiment is operating as a de-interleaver 50, it isassumed that the encoded data is appearing on line 51 and that thecontrol means 59 has locked on to the block sync signals. Thus, controlmeans 59 also recognizes when the de-interleaver 50 is in the linear orsequential mode or is in the quasi-random mode. During the linear orsequential mode the address counter 54 is producing the sequentialaddresses on line 55 and during the quasi-random mode, the addresses arebeing produced by the ROM 62 on line 63 and are delayed one count andthen presented on line 55 to the RAM memory 57 of the de-interleaver.Thus, it is understood that the interleaver and de-interleaver areoperating in exactly identical modes as far as the sequence ofoperations and clock pulses are concerned.

Having explained a preferred embodiment and modified embodimentapparatus capable of operating as either an interleaver orde-interleaver, it will now be understood that the structure 25 and 50shown in FIGS. 3 and 8 are adapted to be substituted into the systemshown in FIG. 1 for the interleaver 13 or the de-interleaver 21.

The schematic tables shown in FIGS. 4 to 7 are not actual memorylocations, but were designed to illustrate the sequence of addresses inthe order in which there are accessed in memory. The final sequence ofaddresses are shown in FIG. 2 illustrating the effectiveness of rotationto achieve a quasi-random sequence of addresses. In actual practice thememory arrays used are much larger than an 8×8 array.

We claim:
 1. A data transmitting system of the type having aninterleaver for changing the order of data bits in a data stream to betransmitted comprising:a data source for providing a stream of data bitsto be transmitted, interleaver means coupled to said stream of databits, transmitter means coupled to said interleaver means fortransmitting said data bits in a quasi-random pattern sequence, saidinterleaver means comprising buffer memory means for storing a block ofsaid stream of said data bits in a predetermined sequential pattern ofmemory addresses, said addresses being definable in terms of an array ofcolumns and rows, first address pointer means coupled to said buffermemory means for generating said predetermined pattern of memoryaddresses and for storing said data bits in said buffer memory means inrows, second address pointer means coupled to said buffer memory meansfor generating a predetermined quasi-random pattern of memory addressesand for reading said stored data bits out of said buffer memory means bycolumns, said predetermined quasi-random pattern of memory addressesbeing generated by a predetermined rotation of bits within columns, andcontrol means coupled to said buffer memory means and said first andsecond pointer means for alternately storing said stream of data bitsinto said buffer memory means as rows of data bits and for reading saidstored data bits out of said buffer memory means as columns of data bitsin a predetermined quasi-random stream of data bits.
 2. A datatransmitting system as set forth in claim 1 which further includesgenerating said predetermined quasi-random pattern of memory addressesby further rotating said bits within rows.
 3. A data transmitting systemas set forth in claim 1 which further includes generating saidpredetermined quasi-random pattern of memory addresses by first rotatingthe order of said columns in said array.
 4. A data transmitting systemas set forth in claim 2 wherein the rotation of bits is a permutation inwhich the new position is equal to the old position plus one multipliedby one-half of the old position.
 5. A data transmitting system as setforth in claim 3 wherein the rotation of columns is a permutation inwhich the new position is equal to the old position plus one multipliedby one-half of the old position.
 6. A data transmitting system of thetype set forth in claim 1 which comprises a forward error correctionencoder coupled between said data source and said interleaver.
 7. A datatransmitting system of the type set forth in claim 6 which furtherincludes;receiving means for receiving said transmitted quasi-randomstream of data bits, de-interleaver means coupled to said receivingmeans for generating said stream of data bits in the same order asgenerated by said data source, and forward error correction decodingmeans coupled to said de-interleaving means coupled to saidde-interleaving means for correcting bit errors in said stream of databits introduced by a burst of high energy interference signals.
 8. Adata transmitting system of the type set forth in claim 1 wherein buffermemory means comprise a random access memory.
 9. A data transmittingsystem of the type set forth in claim 8 wherein said first and secondaddress pointers comprise a counter and a read only memory.
 10. A datatransmitting system of the type set forth in claim 9 wherein saidcounter is adapted to supply the same address to said random accessmemory and to said read only memory.
 11. A data transmitting system ofthe type set forth in claim 10 wherein said read only memory is adaptedto supply an address to said counter.